The inventive concept relates to semiconductor devices having three-dimensional (3D) channels and to methods of fabricating semiconductor devices having 3D channels.
Various techniques have been developed to increase the integration density of semiconductor devices. One current technique is to provide a multi-gate transistor configuration in which a fin-shaped (or nanowire-shaped) silicon body is formed from a substrate, and multiple gates are formed on surfaces of the silicon body to define 3D channel regions within the silicon body.
3D channels facilitate reduction in scale at least partly because it is not necessary to increase a gate length (or channel length) to realize a transistor with relatively adequate current control capability. In addition, a short channel effect (SCE), in which the electric potential of a channel region of a transistor is affected by a drain voltage, can be effectively suppressed.